1. Technical Field
The present disclosure relates to memory devices and methods of manufacturing the same. More particularly, the present disclosure relates to memory devices having improved electrical characteristics and to methods of manufacturing the memory devices.
2. Description of the Related Art
The demand for electrically erasable programmable read only memory (EEPROM) devices and flash memory devices has increased. Flash memory devices may electrically perform programming and erasing operations using hot electron/hole injection or Fowler-Nordheim (FN) tunneling.
Moreover, flash memory devices may be classified into floating gate type memory devices and floating trap type memory devices such as, for example, silicon-oxide-nitride-oxide-silicon (SONOS) memory devices or metal-oxide-nitride-oxide-semiconductor (MONOS) memory devices.
Generally, the floating trap type memory devices include a tunnel insulation layer formed on a semiconductor substrate, a charge trapping layer for trapping electrons or holes moving through a channel region, a blocking layer formed on the charge trapping layer, and a gate electrode formed on the gate electrode.
In the floating trap type memory devices, hot electrons having high energies are injected into a trap site formed in the charge trapping layer to increase a threshold voltage when a data is programmed, whereas hot holes having high energies are injected into the trap site in the charge trapping layer to be recombined with the hot electrons so that the threshold voltage may be decreased when a data is erased. Alternatively, the electrons injected into the charge trapping layer may move to the semiconductor substrate by FN tunneling when data is erased.
A high potential barrier may be formed between the tunnel insulation layer including silicon oxide and the charge trapping layer including silicon nitride. That is, an energy difference of about 3.5 eV may be generated between an energy level of a conduction band of the tunnel insulation layer and that of the charge trapping layer. Additionally, an energy difference of about 4.4 eV may be generated between an energy level of a valence band of the tunnel insulation layer and that of the charge trapping layer. Here, an energy of about 3.5 eV is acquired by hot electrons so that the hot electrons may be injected into the charge trapping layer while programming data, and an energy of about 4.4 eV is acquired by hot holes so that hot holes may be injected into the charge trapping layer while erasing a data. The energy of about 3.5 eV and the energy of about 4.4 eV may be lost so that trap sites may be generated at an interface between the tunnel insulation layer and the semiconductor substrate or in an interior of the tunnel insulation layer. The trap sites may change a threshold voltage, and the electrons or the holes trapped in the charge trapping layer may move into the trap sites. Thus, data retention characteristics of the floating trap type memory devices may be degenerated as programming and erasing operations are repeatedly performed.
To prevent the degeneration of the data retention characteristics, the tunnel insulation layer should be thickly formed. However, when the tunnel insulation layer has a large thickness, electrons or holes may move along a long distance while programming or erasing data. Thus, the speed of data programming/erasing may be decreased and the voltage applied for performing the programming and erasing operations may be increased.
Therefore, there is a need for memory devices which have improved characteristics such as longer data retention time and faster data programming/erasing speeds to thereby prevent the occurrence of the difficulties described above.